VonNeumann
Architecture
(revised
02/25/2008)
Big fleas have little fleas
on their backs to bite 'em
And little fleas have littler fleas
and so on ad infinitum
Levels of Abstraction - Abstraction "ignores the details and concentrates on the essentials".
The "elementary building blocks" of the computer are transistors and gates (AND, OR NOT gates etc). This view of the computer is too low level to see how the computer is organized to execute a program.
Going up one level we can look at the higher level organization where gates are configured into circuits like a ripple carry adder, an n-bit comparator or a multiplexor. Still this is too low-level to see the big picture.
The next level is to look at how units like adders, comparators, multiplexors etc. are organized into function units like an ALU, or Control unit. This lead us to consider the consider the model of the computer called the von Neumann architecture.
The von Neumann Architecture - There are certain fundamental characteristics which are common to all computers from the most inexpensive CPU embedded in an appliance to a super computer.
- There are five major sub-systems
- Input device(s)
- Central Processing
Unit (CPU) or processor
- arithmetic logic unit
(ALU)
- control unit
- Main Memory
- Output device(s)
- Secondary storage (e.g.
hard drives etc)
- Stored Program Concept : Instructions to be
executed are represented in binary and stored in the main memory of the
computer where they can be manipulated like data.
- Instructions are executed sequentially. One
instruction at a time is fetched from memory, decoded, and executed
Memory and Cache
- data is stored in binary representation
- memory is partitioned into fixed length units called memory
cells (the
generic name). Each memory cell is associated with a unique (numeric)
identifier called its address.
- Memory cell sizes have
been 6, 8, 12, 18, 24, 32, 40, 48, and 60 bits long.
- Today the standard
memory cell is an 8-bit cell size called a byte. A word
is usually 4 bytes long (32-bits), a word being the amount of memory used
to store an integer. Early micro-computers used a smaller 16-bit, 2 byte
word size.
- The address space is the maximum number
of possible cell addresses. An n-bit address field generates 2n
addresses.
- Accesses to memory are done by specifying the address,
not the contents. A memory
access either fetches (reads from memory) or stores (writes to memory) the
complete contents of a memory
cell; you can’t access just part of a memory cell. A memory cell is the
smallest unit of information that can be fetched from or stored to memory.
- As noted above, a distinction is made between the address
of a cell and its contents (very much like the distinction between
the variable x and the value of the variable x).
- The two basic memory operations are a non-destructive fetch (read) and a destructive store (write); destructive in that it over-writes the previous contents
of the cell.
- In terms of hardware, access to memory is controlled by
two registers
- MAR or memory address
register holds the address of the memory cell being accessed
- MDR or memory data
register holds the contents of the cell being accessed
Alternately, using a bus to connect memory to the CPU, there are separate Address and Data lines
- Access time is the same for all cells. Today
access time is very fast, anywhere from 50 to 200 nanoseconds (one
nanosecond equals 10 to the minus 9 seconds or 1 billionth of a second)
- Physically memory can be visualized as a numbered list
of cells, similar to an array or list where each components or entry is
uniquely identified by its position (number) i.e. the address in the
list.
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Cache Memory -
Despite the fast speed of memory access, the CPU (Central Processing Unit) is
faster. Faster memory is possible but expensive. Cache memory is a small but
faster (5 - 10 times faster) memory interposed between main memory and
the CPU. When the CPU fetches a cell from main memory, its contents and the
contents of the surrounding cells are copied to cache memory (called a cache
line). Thereafter if the CPU tries to access that same cell (or a cell
close by), it can obtain the contents from the faster cache memory. The reason
this works due to the Principle of Locality which is the observation that when a computer accesses a
memory cell the probability is high that in the near future it will access that
memory cell again (temporal locality) or a memory cell which is near by
(spatial locality). Memory accesses are done in parallel to both the
main memory and the cache. If the access is "satisfied out of cache",
the slower main memory access is aborted. Cache hit ratio is the fraction of memory accesses satisfied out of cache.
Cache hit ratios of 90% or above are not uncommon.
Input/Output and Secondary (Mass) Storage
Input/Output poses significant problems for computers - mainly trying to synchronize a very fast computer with the very slow (relatively speaking) I/O device. There is also the problem of number conversion. Human readable numbers are strings of ASCII coded digits while numbers stored internally in a computer are encoded in binary integer representation or in floating point representation. Recall that in Python when you read a text file, everything is read in as a string type; your program must use the int() or float() type conversion functions to convert the strings of digits to integers or floating point numbers. Doing I/O may require numeric conversion from ASCII strings of digits to internal binary representation and back.
I/O devices include keyboards, "pointing" devices (mouse, track ball), display monitors, printers, magnetic tapes (or tape cartridges disk drives (hard or floppy), CD-ROMs etc. The later devices like disk drives and CD-ROMs are also used as secondary (mass) storage.
Storage is either volatile or non-volatile. Main memory is volatile in that if the power goes off the contents of main memory is lost. Secondary storage is non-volatile in that when the power is off the contents are not lost.
Devices like keyboards, display monitors, and printers are human readable where as devices like disk drives and CD-ROMs are machine readable. The latter devices can store information in internal binary representation thus removing the need to convert numbers from ASCII digits to internal binary representation.
DASD (Direct Access Storage Device) devices are devices like hard disks and CD-ROMs. Data is stored as fixed sized blocks of data called sectors which can be accessed by a unique address. On a hard drive, fixed sized sectors (e.g. 512 byte sector is a common size) are arranged in concentric circular tracks on the surface of a disk. A read/write head can be positioned radially to access a given sector. Sectors are addressed by sector number within track (or cylinder) number within read/write head number A disk has at least two r/w heads (top and bottom). A hard drive has at least 2 disks for 4 r/w heads.
Time to access a given sector is broken down into seek time (time to position the r/w head laterally across the radius of the disk), latency (time required for the beginning of the sector to rotate until it's under the r/w head) and transfer time (time for entire sector to pass under the r/w head). Unlike SASD devices (see below) DASD access to any given sector is relatively "fast" and access to any sector is independent of every other sector. However, access is very slow when compared to CPU speeds.
SASD (Sequential Access Storage Device) devices are devices like tape units. Access is sequential in that to access the nth record, you must first access the first n-1 records. Thus access to any record depends on accesses all previous records first. SASD devices are relatively inexpensive and have a high data capacity but are very slow if you are trying to access a particular record. They make very good back-up devices.
I/O devices are very slow with respect to a CPU. With access times in the micro-seconds (thousandths of seconds) for an I/O device and speeds in the nanoseconds (billionth of seconds) for a CPU, the speed differential between an I/O device and a CPU may be a factor of 100,000 (5 orders of magnitude!).
I/O controllers An I/O controller is a small inexpensive "computer" which handles to I/O for the CPU. Data is passed between the CPU and an I/O buffer in the I/O Controller at electronic speeds. Then the data is transferred between the I/O controller and the I/O device freeing the CPU to do something else. When the transfer of data between the I/O controller and I/O device is complete, the I/O controller interrupts the CPU to inform it that the transfer is complete. The CPU can take it from there.
The Central Processing Unit (CPU): ALU + Control Unit
- The ALU is formed around a data path consisting of
- registers - temporary high speed
storage locations in the CPU (apart from the main memory)
- ALU circuitry to perform arithmetic
and logical operations
- buses to connect the
register to the ALU circuitry and the results back to the registers
- There is only a small number of registers
- registers are generally
named. For example the Intel 80x86 architecture has registers
named AX, BX, CX, and DX
- registers can be general
purpose - used to store the temporary results of calculations
- registers can be special
purpose - used to store environment data (e.g. the address of the
next instruction or the current instruction)
- ALU circuitry performs all functions in parallel but
only the one result is selected to be stored (see Fig 5.12)
The Control Unit
- code execution is built around a fetch-decode-execute
cycle which
makes use of two special purpose registers: the Program
Counter
(PC) register which holds the address of the next instruction to be
executed, and the Instruction Register (IR) which holds the current instruction.
- Fetch: Using the address
contained in the PC, the instruction at this address is fetched from
memory to the IR. The PC is incremented to contain the address of
the next instruction
- Decode: The instruction in
the IR is decoded.
- Execute: The instruction is
executed
- Instruction Format: the format of an instruction is
operation code (called op-code) followed by one or more addresses for the operands
(data operated on by op-code). All op-codes and operands (addresses) are
in binary
- the op-code part is
decoded in the IR
- the address(es) part is
gated to the MAR if the instruction requires that data be fetched from or
stored to memory
- Instruction Types - machine instructions can be classified
into a number of types. A few are given below
- data transfer - data is
moved between memory and CPU registers (load and store) or between CPU
registers
- arithmetic - addition,
subtraction, multiplication, division
- comparisons - two
values are compared and "flags" (special bits) are set/cleared
depending on the outcome (equal, less than, greater than) or the sign of
the accumulator is tested
- branch - von Neumann
architecture executes instructions sequentially (the PC always points to
the next instruction to be executed). Branch instructions allow a program
to alter the contents of the PC register so the next instruction can be
fetched from a different location in memory.
- RISC vs CISC
design philosophies
- CISC (Complete/Complex
Instruction Set Computer) has a large set of complex but slow
instructions.
- RISC (Reduced
Instruction Set Computer) has a smaller set of simpler but faster
instructions. Complex operations are performed by sequences of simpler
operations.
Putting the Pieces Together: Having described the components of a von-Neumann architecture, we examine the details of the Fetch-Decode-Execute cycle. Note how each "phase" is sub-divided into data movements between registers contained in the data path..
The Fetch Phase
- PC -> MAR : send the address of the next instruction
to MAR register
- fetch : issue a memory fetch signal
- MDR -> IR : move instruction from MDR register to Instruction
Register
- PC + 1 -> PC : increment contents of PC to point to
address of next instruction
The Decode Phase
- IR(op) -> decoder unit : decode the instruction in
the Instruction Register
The Execute Phase (what happens depends
on decoded instruction)
- LOAD X
- IR(addr) -> MAR :
move operand address to MAR
- fetch : issue a memory
fetch signal
- MDR -> Accumulator :
move contents of MDR (operand) to accumulator
- STORE X
- IR(addr) -> MAR :
move operand address to MAR
- ACC -> MDR : send
contents of Accumulator to MDR
- store : issue a memory
store signal
- ADD X
- IR(addr) -> MAR move
operand address to MAR
- fetch : issue a memory
fetch signal
- ACC <- MDR + ACC:
add (via ALU) contents of MDR (operand) and Accumulator storing
results in Accumulator
- JUMP X
- IR(addr) -> PC :
move address in IR to PC
- JNEG X (jump to address X if Accumulator is
negative)
- If ACC < 0
- IR(addr) -> PC :
move address in IR to PC
- Else Do Nothing