Addressing modes are the ways one can compute an effective address where the effective address is the address of operand used by instruction.

Addressing modes can be considered either from a functional point of view (i.e. an  assembler language p.o.v.) or an implementation point of view (a machine language p.o.v.). For example from a functional p.o.v. the PDP-8 instruction TAD X is an example of direct addressing (the effective address is part of the instruction). But from an implementation p.o.v. the PDP-8 supports two direct addressing modes, zero page and current page addressing, which implement different methods to calculate the effective address.

Classifying Instructions According to Number of Operands

• Zero Address - any stack architecture - e.g.. IJVM Mic -1
• One Address - accumulator is implicit operand - e.g. PDP-8, IAS
• Two Address - one operand is both source and destination - e.g. Intel 80x86
• Three Address - two source operands and one destination operand
• VAX has 3 address instructions (a good example of a CISC architecture)
• ARC has 3 register instructions (a good example of RISC architecture)
• Four Address - 4th operand is either address of next instruction (obsolete technique) or for some reason the instruction requires more than three operands (eg integer division produces quotient and remainder)

The "Standard" Addressing Modes - A Functional View

EAddr denotes "effective address"; C( ) denotes "contents of" or "contents at".

Binding time refers to the latest time that the effective address can be fixed

The value of the Operand Field of an instruction can be considered as either an Address or a Displacement value

• Immediate Mode (level 0) - operand is part of instruction; i.e. operand contained in Operand Field - binding time is at assembly time: ARC, IJVM, and Intel 80x86 
• Register Addressing (level 1/2?) - operand contained in register - binding time is assembly time: ARC, Intel 80x86
• Direct (level 1) - effective address is part of instruction or directly obtained (calculated) from instruction - binding time is assembly time: PDP-8, ARC, IJVM, Intel 80x86
• Indirect (level 2) - sometimes called "deferred"; operand field of instruction contains address of the address of the operand. This is like a "pointer" which can be modified -binding time is run time.
• Register Indirect Addressing - effective address of operand contained in a register
EAddr = C(Reg)
ARC, Intel 80x86

• Memory Indirect Addressing - effective address of operand contained in a word in memory
Operand Field contains an Address so EAddr = C(Address)
PDP-8
• Indexed or Base (or Index)) + Offset (Indirect) or Register + Offset (Indirect):  Level 1 1/2- effective address obtained by adding value of operand field or offset  to contents of register - EAddr = C(Reg) + Offset  - binding time is run time
  
Sometimes called displacement addressing
• Array Type: Fixed Base (address) + Variable Register Offset
Operand Field contains a base Address so EAddr = base Address + C(Reg)
used to implement arrays

• Record Type: Fixed Register + Variable Offset (address)
Operand Field contains a Displacement so EAddr = C(Reg) + Displacement
used to implement records and stack frames (local variables for subroutines)

• Program Counter Based: PC + offset : relative addressing
Operand Field contains a Displacement so EAddr = C(PC) + Displacement
Near and Short Jump instructions on the Intel 80x86 use this

• Base + Index (Indirect) or Double Indexed (Indirect): Level 1 1/2 - effective address is obtained by adding the contents of two registers - EAddr = C(Reg1)+C(Reg2) - binding time is run time: ARC, Intel 80x86:  
• Base + Index + Offset (Indirect) - Level 1 1/2 -  effective address obtained by adding contents to two registers plus an offset - EAddr = C(Reg1) + C(Reg2) + offset - binding time is run time: Intel 80x86.
  
• Indexed With Scaling : Base + Register Offset * Scaling Factor - binding time is run time
• variant of Indexing useful for array calculations where size of component is multiple bytes long
• Operand Field contains base Address then EAddr = base Address + C(Reg) * Scaling Factor
• Auto-indexing : Register Indirect or Indexing with auto-increment/decrement of register
• Auto-Increment:: EAddr = C(Reg); Reg = C(Reg) + 1. Note indirect-increment order!
• Auto-Decrement: Reg = C(Reg) - 1; EAddr = C(Reg). Note decrement-indirect order!
• PDP-8 auto-indexing mode increments then uses indirection; IReg = C(IReg) + 1; EAddr = C(IReg)
• Stack Addressing : push & pop - a variant of register indirect with auto-increment/decrement using the SP register implicitly
• Push: EAddr = C(SP). SP = C(SP) -1 ; C(C(SP)) = Source - auto-decrement!
• Pop: EAddr = C(SP); Destination = C(C(SP)); SP = C(SP) + 1; - auto-increment

Some "Not-So-Standard" Addressing Modes

• Auto-increment/Auto-decrement Indirect
• EAddr = C(C(Reg)); Reg = C(Reg) + 1; PDP-11 Mode 3 Addressing
  
The PDP-11 used the PC as the register to implement direct addressing this way!
• Reg = C(Reg) - 1; EAddr = C(C(Reg)); PDP-11 Mode 5 Addressing
• Index 80x86 Supports this using Base Registers (BX, BP) and Index Registers (SI, DI)
• Indexing Indirect : Indexing coupled with indirection (rare?)
• post-indexing: indexing after indirection: EAddr = C(Address) + C(Reg)
• pre-indexing: indirection after indexing: EAddr = C(Address + C(Reg))
• Multiple Indirection : requires indirect bit as part of address field (PDP-10 could do this)

Stack Operations

• Stacks generally start at high address memory and grow upward!
• Implementation of Push and Pop Operations
• PUSH : decrement stack pointer and store operand at effective address contained in stack pointer
• POP : extract operand from effective address stored in stack pointer and increment stack pointer
• Uses for a Stack
• Temporary Storage
• Reversing Strings
• Evaluation of Reverse Polish Notation (RPN) Expressions
• Infix to Reverse Polish Notation Conversion
• Subroutine Calls
• Zero Address Instructions

Addressing Examples

• PDP-8
• Zero/Current Page Direct
• Memory Indirect (indirect bit set)
• auto-indexing (increment then indirect)
• ARC : For memory referencing from the implementation p.o.v. the ARC implements Base + Index and Base + Offset addressing. However with %r0 always equaling 0. Arithmetic instructions support immediate mode and register addressing 
• Direct - e.g. ld [x], %r3 implemented as ld %r0, [x], %r3
• Register indirect - e.g. ld %r1, %r3 implemented as ld %r1, %r0, %r3
• Indexed or Base + Offset - e.g. ld %r1+x, %r3 
• Double Indexed or Base + Index - e.g. ld r1%, r2%, %r3
• Immediate Addressing (arithmetic format) - e.g. addcc r1%, 4, %r1
• Register Addressing - e.g. addcc %r1, %r2, %r3
  
• PDP-11 : The PDP-11 was a two-address, 16-bit word machine with 8 registers R0 - R7 and 8 addressing modes.
• Mode 0 - register addressing
• Mode 1 - register indirection
• Mode 2 - auto-increment (register contains effective address; then increment register)
• Mode 3 - auto-increment indirect (register is pointer to effective address; then increment register)
• Mode 4 - auto-decrement (decrement register; register now contains effective address)
• Mode 5 - auto-decrement indirect (decrement register; register now is pointer to effective address)
• Mode 6 - indexing (register plus 16 bit word following is effective address- “array type”)
• Mode 7 - indexing indirect (register plus 16 bit word following is pointer to effective address)

The "even" modes add a level of indirection to the previous "odd" modes. For example, in Mode 7 the contents of a register plus offset is not the effective address but a pointer to the effective address.

On the PDP-11 R6 was the Stack Pointer and R7 was the Program Counter. Using these registers with some of the above addressing modes created some "standard" and some unusual addressing modes.

    Examples :    Mode 2 Register 7 = immediate mode
                  Mode 3 Register 7 = direct addressing
                  Mode 6 Register 7 = self relative addressing
                  Mode 2 Register 6 = pop
                  Mode 4 Register 6 = push

Addressing Modes for the Intel 80x86 Architecture

• Simple Addressing Modes (3)
• Immediate Mode : operand is part of the instruction

    Example:   mov ah, 09h
    
               mov dx, offset Prompt

• Register Addressing : operand is contained in register

    Example:   add ax, bx

• Direct : operand field of instruction contains effective address
 

    Example:   add ax, a

• Register Indirect Mode - contents of register is effective address

    Example     mov bx, offset Table 
                add ax, [bx]

• Only the base registers BX, BP and the index registers SI, DI can be used for register indirect addressing. However for reasons give below do not use the BP register.

 
• Register indirect can be used to implement arrays

    Example     To sum an array of word-length integers

                       mov cx, size  ; set up size of Table
                       mov bx, offset Table  ; BX <- address of Table
                       xor ax, ax    ; zero out Sum
                Loop1: add ax, [bx]  
                       inc bx        ; words are 2 bytes long
                       inc bx
                       loop loop1

• Push and Pop instructions are implemented using register indirection with the SP register.
• The DS segment register is used with the BX, SI, and DI registers. However since the SS segment register is used with the BP, using BP for register indirection will access the stack and not the data segment.

 
• Base + Offset Indirect or Index + Offset Indirect

The effective address is obtained by adding the offset value contained in the operand field of the instruction to the contents of a register

   Example     add ax, Table[bx]

Here the effective address is obtained by adding the value Table (not the contents stored at location Table) to the BX register. This is the effective address.
 
• Base + Offset Indirect (Index + Offset Indirect) makes use of the Base registers BX and BP (but avoid BP for reasons given above) or the Index registers SI and DI.
• Base + Offset Indirect provides an alternate method for inplementing arrays

    Example           mov cx, size   ; set up size of Table
                      xor bx, bx     ; BX <- 0 for zero offset
                      xor ax, ax     
               Loop2: add ax, Table[bx] 
                      inc bx             ; words are 2 bytes long
                      inc bx
                      loop Loop2

• Array Implementation - Offset contains fixed value (usually address of zeroth byte in array) while the contents of the Base register is incremented to compute offset addresses within array. See above example.
• Record Implementation - Fields within records are accessed as fixed offsets from the Base address of the record. For example a record might consist of a integer field (2 bytes) followed by a character field (1 byte) followed by a 12 bytes string field. Offsets for the integer field, character field and string field are 0, 2 and 3 respectively. Thus to access the character field use

            mov bx, offset Record
            mov al, [bx]+2

• Syntax for Base + Offset Indirect Addressing. The following are equivalent

            add ax, Table[bx]
            add ax, [Table+bx]
            add ax, Table+[bx]
            add ax, [bx]+Table

• Base + Index + Offset Indirect

The effective address is obtained by adding the contents of a Base register (BX or BP but avoid BP) to the contents of an Index register (SI or DI) plus an offset (operand field of instruction).  That is

EAddr <- C(Base Reg) + C(Index Reg) + Offset.

 

• Relative (branch instructions only) : IP <- IP + offset; same as relative addressing

Additional Pentium & Power PC Addressing Modes

    Pentium (additional modes)

•     Scaled Index with Displacement : EAddr = C(Index) * Scaling Factor + Offset
•     Base with Scaled Index and Displacement: EAddr =  C(Index) * Scaling Factor + C(Base) + Offset

•     Immediate : operand part of instruction
•     Register : operand contained in register
•     Indirect : EAddr = C(Base Reg) + displacement (load/store)
•     Indirect Indexed : EAddr = C(Base Reg) + C(Index Reg)  (load/store)

What is Really Used

• Auto-indexing - push & pop procedure parameters
• Direct - global variables
• Immediate - constants
• Index - data structures like array & records; accessing local variables
• Register - holding local variables
• Register Indirect - pointers to structures (e.g. arrays & records)

Design Issues for Addressing Modes

• Orthogonality
• Load/Store Architectures
• CISC (many addressing modes) vs RISC (few addressing modes)

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